Abstract: During the last few decades, advances in electronic packaging have supported and sustained significant growth across computing, networking and data management ecosystems. Emerging applications and increased competition will drive an extremely diverse set of 2D, 2.5, 3D packaging architectures and designs, requiring novel material technologies and manufacturing processes. The area of heterogeneous packaging, assembly and test will continue to require significant improvements in the collaterals required for time-sensitive, cost-effective, and 'smart' technologies.
This drives the need to define, develop and deploy cost-effective solutions that balance the need for increased integration and enabling the right level of product differentiation. Rigorous assessments with the appropriate quantification and understanding of multiple trade-offs across performance, manufacturing complexity, yield and cost need to be comprehended for the right decisions to be made on different options and the degree of component integration vs. product differentiation.
Challenges need to be addressed for facilitating the effective analysis and characterization to facilitate efficient design, materials selection and associated assembly and test manufacturing processes. The role of inter-disciplinary solutions and the need for new competencies will be highlighted, including recent trends in technologies, advanced analysis / simulation tools and metrologies and their applications to electronic packaging. This includes the analysis, characterization, validation and optimization of the different steps of the design, assembly manufacturing and test equipment and processes, and the design / materials used to meet mechanical integrity, reliability, high speed signal integrity, power delivery and thermal dissipation requirements.
Biography: Gaurang joined Intel in 1988 after receiving his PhD degree and during his 30+ year tenure at Intel, he has contributed to various areas including mechanical analysis and testing, electrical and physical design and analysis of multi-chip modules, design/analysis tool development for packages/boards, and thermal technologies and solutions. The scope of his group currently includes materials selection and characterization, dimensional measurements, and modeling and validation related to structural integrity, power delivery, high speed signaling, thermals and heat dissipation, and fluid flow to support the design and development of electronic packaging, assembly and test technologies. The group has teams and labs in Chandler, Oregon and Malaysia. He is a recipient of the Intel Achievement Award and serves on national advisory / review boards.
Abstract: Modern electrified mobility demands increased levels of electrical power, thereby putting mounting strains on the concomitant thermal management. These trends can be seen across a variety of mobility modalities. This talk will present results on the management of thermal loads from a systems perspective with a focus on complex systems having multiple interconnected subsystems; these subsystems include thermal sources, sinks, transport, heat exchange interfaces, and storage elements. The overall systems also include the interaction with the electrical components providing the source of the thermal loads. First, we introduce a graph-based framework that is useful for understanding the complex interconnections within these systems. Subsequently, we will present numerical design optimization approaches that exploit the mathematical formulation resulting from the graphs to select vehicle topology as well as component sizing while considering both static design and dynamic control. This optimization approach includes the co-design of the electrical and thermal, or electro-thermal, systems rather than the more typical sequential design of electrical systems dictating thermal requirements. Thirdly, a control approach for the complex electro-thermal class of systems using a hierarchical approach will be presented. The hierarchical framework allows for the simultaneous management of both the electrical and thermal power. The presentation will include design examples from the automotive and aerospace domains.
Biography: Andrew Alleyne received his B.S.E. from Princeton and his M.S./Ph.D. degrees, respectively, from UC Berkeley. He joined the University of Illinois, Urbana-Champaign in 1994 where he currently holds the Ralph and Catherine Fisher Professorship and is the Director for the NSF Engineering Research Center on Power Optimization for Electro-Thermal Systems (POETS). His research focuses on the modeling, simulation and control of nonlinear mechanical systems with a current focus on transient thermal system. He developed a commercial simulation tool, ThermosysTM, for simulation of refrigeration systems and worked with the Air Force Research Laboratory to develop the Aircraft Transient Thermal Modeling and Optimization toolbox. His academic record includes supervision of over 80 M.S. and Ph.D. students and over 400 conference and journal publications. He has been a Distinguished Lecturer of the Institute for Electronic and Electrical Engineers (IEEE) and a National Research Council (NRC) Associate. He was a Fulbright Fellow to the Netherlands and has held visiting Professorships at TU Delft, University of Colorado, ETH Zurich, and Johannes Kepler University. He is a Fellow of IEEE and ASME and currently serves on the Scientific Advisory Board for the U.S. Air Force and the National Academies Board On Army Research and Development.
Abstract: The end of Moore's Law scaling coupled with the proliferation of data brought on by an increasing array of devices at the edge of the network is forcing a fundamental shift in computer architecture. For over 65 years classical Von Neumann architecture, where computational elements like CPUs make up the core of any system, are giving way to new architectures where memory is the dominant element surrounded by a heterogeneous mix of computational devices that are increasingly being constructed to serve specific, rather than general, workloads. These new architectures offer fewer constraints on design resulting in the creation of a number of unique devices that place new challenges on traditional architectural elements like communication fabrics, data storage and even the way in which computations are performed at the fundamental level. This talk will introduce some of these new elements and the workloads that drive their design. Particular emphasis will be placed on advances in photonics, computational accelerators and computer architecture.
Biography: Cullen is a Vice President of R&D at Hewlett Packard Labs and currently serves as Director of the Systems Architecture Lab where he leads a multi-disciplinary team of researchers investigating computer architecture ranging from data centers to distributed systems. His team focuses on a wide range of inter-related topics including system and fabric architecture, system software, photonics, IC packaging, energy and thermal sciences, and software-hardware co-design. Cullen will also be serving as General Chair of IEEE's International Conference on Rebooting Computing in November of 2019.